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Linear公司的LTCR2145-14/LTC2144-14/LTC2143-14是低功耗2路同時(shí)取樣的14位模數(shù)轉(zhuǎn)換器(ADC),SNR達(dá)到73.1dB,SFDR為90dB,取樣速率達(dá)125Mbps,DC指標(biāo)包括±1LSB INL, ±0.3LSB DNL,整個(gè)溫度范圍內(nèi)不會(huì)丟失碼,CMOS輸出擺幅從1.2V到1.8V,主要用在通信,蜂窩基站,軟件定義無(wú)線電(SDR),手提醫(yī)療圖像設(shè)備,多路數(shù)據(jù)采集和非破壞性測(cè)試.本文介紹了LTC2145-14主要特性, 功能方框圖,典型應(yīng)用電路以及輸入頻率5MHz-150MHz, 150MHz-250MHz和大于250MHz的前端電路圖, 1620A演示板電路圖和材料清單(BOM). The LTCR2145-14/LTC2144-14/LTC2143-14 are 2-channel simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.1dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is 1.2LSBRMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. LTC2145-14主要特性: Two-Channel Simultaneously Sampling ADC 73.1dB SNR 90dB SFDR Low Power: 189mW/149mW/113mW Total 95mW/75mW/57mW per Channel Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 750MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 64-Pin (9mm × 9mm) QFN Package LTC2145-14應(yīng)用: Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing 
圖1.LTC2145-14功能方框圖
圖2.LTC2145-14輸入頻率5MHz-150MHz的前端電路圖
圖3.LTC2145-14輸入頻率150MHz-250MHz的前端電路圖
圖4.LTC2145-14輸入頻率大于250MHz的前端電路圖
圖5.LTC2145-14采用高速差分放大器的前端電路圖
圖6.LTC2145-14典型應(yīng)用電路圖 1620A演示板 Demonstration circuit 1620A supports a family of 16-/14-/12-bit, 25Msps to 125Msps ADCs. Each assembly features one of the following devices: LTC®2185, LTC2184, LTC2183, LTC2182, LTC2181, LTC2180, LTC2145-14, LTC2144-14, LTC2143-14, LTC2142-14, LTC2141-14, LTC2140-14, LTC2145-12, LTC2144-12, LTC2143-12, LTC2142-12, LTC2141-12, or LTC2140-12 high speed, high dynamic range ADCs. Demonstration circuit 1620A supports the LTC2185/LTC2145 family DDR LVDS output mode. The versions of the 1620A demo board supporting the LTC2185 and LTC2145 series of A/D converters. Depending on the required resolution and sample rate, the DC1620A is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 70MHz. Refer to the data sheet for proper input networks for different input frequencies.
圖7.1620A演示板外形圖
圖8.1620A演示板電路圖(1)
圖9.1620A演示板電路圖(2) 1620A演示板材料清單(BOM):
詳情請(qǐng)見(jiàn): http://cds.linear.com/docs/Datasheet/21454314p.pdf 和 http://www.linear.com/demo/DC1620A-G |
