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Lattice公司的MachXO系于是非易失可無限次配置的可編程邏輯器件(PLD),具有256到2280個LUT,I/O數多達271個,多達27.6Kb sysMEM嵌入區塊RAM(EBR)和多達7.7Kb的分布式RAM,支持IEEE 標準1149.1 邊界掃描,工作電壓而不服.3V,2.5V,1.8V或1.2V.主要用在低密度的工業控制,醫療電子,汽車電子,通信和消費電子等領域.本文介紹了MachXO 系列主要特性以及MachXO™ Mini 開發套件主要特性與MachXO™ Mini評估板方框圖,電路圖和材料清單. The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device. Designed for a broad range of low density applications including system control designs, the MachXO PLD family is used in a variety of end markets including consumer, automotive, communications, computing, industrial and medical. The MachXO is optimized to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. MachXO 系列主要特性: Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and non-volatile memory programmable through JTAG port • Supports background programming of non-volatile memory Sleep Mode • Allows up to 100x static current reduction TransFR™ Reconfiguration (TFR) • In-field logic update while system operates High I/O to Logic Density • 256 to 2280 LUT4s • 73 to 271 I/Os with extensive package options • Density migration supported • Lead free/RoHS compliant packaging Embedded and Distributed Memory • Up to 27.6 Kbits sysMEM™ Embedded Block RAM • Up to 7.7 Kbits distributed RAM • Dedicated FIFO control logic Flexible I/O Buffer • Programmable sysIO™ buffer supports wide range of interfaces: LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL PCI LVDS, Bus-LVDS, LVPECL, RSDS sysCLOCK™ PLLs • Up to two analog PLLs per device • Clock multiply, divide, and phase shifting System Level Support • IEEE Standard 1149.1 Boundary Scan • Onboard oscillator • Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply • IEEE 1532 compliant in-system programming MachXO 系列產品: 
MachXO™ Mini 開發套件 MachXO™ Mini Development Kit This user’s guide describes how to start using the MachXO Mini Development Kit, an easy-to-use platform for eval uating and designing with MachXO PLDs. Along with the evaluation board and accessories, this kit includes a pre-loaded Mini System-on-Chip (SoC) demonstration design based on the LatticeMico8™ microcontroller. MachXO™ Mini 開發套件包括: The MachXO Mini Development Kit includes: • MachXO Mini Evaluation Board – The Mini board is a small board (about the size of a business card) with the following on-board components and circuits: – MachXO LCMXO2280C-4TN144C – 2-Mbit SPI Flash memory – 1-Mbit SRAM – I2C temperature sensor – USB connectors (JTAG, RS-232) – 2x16 expansion header for general I/O, I2C, and SPI – Push-buttons for sleep mode and global set/reset – 4-bit DIP switch – DAC/ADC circuit MachXO Sleep Mode circuit Eight status LEDs • Pre-loaded Reference Designs and Demos– The kit includes a pre-loaded demo design (Mini SoC) that inte-grates several Lattice reference designs including the LatticeMico8 microcontroller, SRAM controller, I2C control-ler, SPI Flash memory controller, and a UART peripheral. Firmware supports a temperature monitor demo and, when connected to a host PC, allows you to use a terminal program to use advanced demonstrations. • Two USB Connector Cables – The Mini board is powered from the mini B USB port (DEBUG) when connected to a host PC. The DEBUG port provides a general communication and debug port via a USB-to-RS-232 physical channel. A second USB channel (PROG) provides a programming interface to the MachXO JTAG port. • QuickSTART Guide – The MachXO Mini Development Kit QuickSTART Guide provides information on connect-ing the Mini board, installing Windows hardware drivers, and running the basic temperature monitor demo. • MachXO Mini Development Kit Web Page — The MachXO Mini Development Kit web page on the Lattice web site provides access to the latest documentation, demo designs and drivers for the kit.
圖1.MachXO™ Mini評估板外形圖
圖2.MachXO™ SoC方框圖
圖3.MachXO™ Mini評估板方框圖
圖4.MachXO™ Mini評估板電路圖(1)
圖5.MachXO™ Mini評估板電路圖(2)
圖6.MachXO™ Mini評估板電路圖(3)
圖7.MachXO™ Mini評估板電路圖(4)
圖8.MachXO™ Mini評估板電路圖(5)
圖9.MachXO™ Mini評估板電路圖(6)
圖10.MachXO™ Mini評估板電路圖(7)
圖11.MachXO™ Mini評估板電路圖(8) MachXO™ Mini評估板材料清單:
詳情請見: 
DS1002[1].pdf
(1.36 MB)
EB41[1].pdf
(1.26 MB)
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