標(biāo)題: 上海需要一位 資深A(yù)SIC設(shè)計(jì)師(Principle level ASIC design) [打印本頁(yè)] 作者: KT咨詢 時(shí)間: 2015-6-24 13:41 標(biāo)題: 上海需要一位 資深A(yù)SIC設(shè)計(jì)師(Principle level ASIC design) 【獵頭職位：上海需要一位 資深A(yù)SIC設(shè)計(jì)師(Principle level ASIC design) 】聯(lián)系人：Tina-Wei，郵箱：hr@kthr.com，微信也可查詢職位啦！打開(kāi)手機(jī)微信，搜號(hào)碼“KTHR_COM”或查找微信公眾帳號(hào)“KT人才”或掃描以上二維碼即可添加，歡迎大家關(guān)注！ Responsibility： Module level design and verification activities including:
· Chip level or module level architecture/micro architecture definition；
· ASIC design methodology and flow development；
· Design digital control or datapath logic using Verilog HDL；
· Supervising junior engineers.
Qualification
· BS or MS degree in EE；
· Solid understanding of digital chip design basics in terms of datapath, control, clocking, synthesis, timing etc；
· Familiar with common EDA tools in ASIC design；
· Extensive knowledge of Verilog, System Verilog, C and scripting languages；
· 10 years of experience；
· Extensive experience with networking products such as switches, network processors, home gateway, MAC, etc；
· Familiar with Ethernet technology and TCP/IP protocol.
